library ieee; 
use ieee.std_logic_1164.all; 
 

entity mux is

  port (a, b, c, d : in std_logic_vector (3 downto 0); 
        s : in std_logic_vector (1 downto 0); 
        o : out std_logic_vector (3 downto 0)); 
end mux; 
 
architecture archi of mux is 
  begin 
    process (a, b, c, d, s) 
    begin 
      case s is 
        when "00" => o <= a; 
        when "01" => o <= b; 
        when "10" => o <= c; 
        when others => o <= d; 
      end case; 
  end process; 
end archi; 

